Method for preparing semiconductor device structure with series-connected transistor and resistor

ABSTRACT

A method for preparing a semiconductor device structure is provided. The method includes forming an isolation structure in a semiconductor substrate, and recessing the semiconductor substrate to form a first opening and a second opening. The first opening and the second opening are on opposite sides of the isolation structure, and a width of the second opening is greater than a width of the first opening. The method also includes forming an electrode layer over the semiconductor substrate. The first opening and the second opening are filled by the electrode layer. The method further includes polishing the electrode layer to form a gate electrode in the first opening and a resistor electrode in the second opening, and forming a source/drain (S/D) region in the semiconductor substrate. The S/D region is between the gate electrode and the isolation structure

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. Non-Provisional application Ser. No. 16/832,118 filed Mar. 27, 2020, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a method for preparing a semiconductor device structure, and more particularly, to a method for preparing a semiconductor device structure with a set of series-connected transistor and resistor.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while providing greater functionality and including greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, various types and dimensions of semiconductor devices providing different functionalities are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices.

However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations. Integration in semiconductor devices becomes increasingly complicated. An increase in complexity of manufacturing and integration of the semiconductor device may cause problems. For example, a shrinking resistor formed by a conventional process flow may have an insufficient sheet resistance. Accordingly, there is a continuous need to improve the manufacturing process of semiconductor devices so that the problems can be addressed.

This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.

SUMMARY

In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a gate electrode and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.

In an embodiment, the semiconductor device structure further includes a well region disposed in the semiconductor substrate, wherein the resistor electrode is disposed over the well region.

In an embodiment, the well region adjoins the isolation structure.

In an embodiment, the semiconductor device structure further includes a dielectric layer disposed over the semiconductor substrate, wherein a first portion of the dielectric layer extends between the gate electrode and the semiconductor substrate.

In an embodiment, a second portion of the dielectric layer extends between the resistor electrode and the semiconductor substrate.

In an embodiment, the semiconductor device structure further includes an inter-layer dielectric (ILD) disposed over the semiconductor substrate, and an interconnect structure disposed over the ILD layer, wherein the S/D region is electrically connected to the resistor electrode through the interconnect structure.

In an embodiment, the semiconductor device structure further includes a conductive structure disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure, and an inter-layer dielectric (ILD) disposed over the semiconductor substrate, wherein the conductive structure is covered by the ILD layer.

In another embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a gate electrode and a resistor electrode disposed in a semiconductor substrate. A dopant concentration of the gate electrode is greater than a dopant concentration of the resistor electrode. The semiconductor device structure also includes an isolation structure disposed in the semiconductor substrate. The gate electrode and the resistor electrode are separated by the isolation structure. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.

In an embodiment, a width of the resistor electrode is greater than a width of the gate electrode.

In an embodiment, the semiconductor device structure further includes a well region disposed in the semiconductor substrate, wherein the resistor electrode is disposed over the well region, and a conductivity type of the well region is the same as a conductivity type of the S/D region.

In an embodiment, the semiconductor device structure further includes a dielectric layer disposed over the semiconductor substrate, wherein the gate electrode is separated from the semiconductor substrate by a first portion of the dielectric layer, and the resistor electrode is separated from the well region by a second portion of the dielectric layer.

In an embodiment, the isolation structure is covered by the dielectric layer.

In an embodiment, the semiconductor device structure further includes a conductive structure disposed in the semiconductor substrate and over the isolation structure, wherein the conductive structure is in direct contact with the S/D region and the resistor electrode.

In yet another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming an isolation structure in a semiconductor substrate, and recessing the semiconductor substrate to form a first opening and a second opening. The first opening and the second opening are on opposite sides of the isolation structure, and a width of the second opening is greater than a width of the first opening. The method also includes forming an electrode layer over the semiconductor substrate. The first opening and the second opening are filled by the electrode layer. The method further includes polishing the electrode layer to form a gate electrode in the first opening and a resistor electrode in the second opening, and forming a source/drain (S/D) region in the semiconductor substrate. The S/D region is between the gate electrode and the isolation structure.

In an embodiment, the method further includes forming a well region in the semiconductor substrate before the first opening and the second opening are formed, wherein a bottom surface of the well region is higher than a bottom surface of the isolation structure, and the second opening is formed by removing an upper portion of the well region. In an embodiment, a sidewall of the isolation structure is exposed by the second opening after recessing the semiconductor substrate.

In an embodiment, the method further includes depositing a dielectric layer over the semiconductor substrate before the electrode layer is formed, wherein the dielectric layer extends into the first opening and the second opening.

In an embodiment, the method further includes performing an ion implantation process on the electrode layer before the electrode layer is polished.

In an embodiment, the method further includes forming an inter-layer dielectric (ILD) over the semiconductor substrate, etching the ILD layer to form a third opening exposing the S/D region and a fourth opening exposing the resistor electrode, and forming an interconnect structure in the openings and over the ILD layer, wherein the interconnect structure is used to electrically connect the S/D region and the resistor electrode.

In an embodiment, the method further includes etching an upper portion of the isolation structure to form a fifth opening after the electrode layer is polished, and forming a conductive structure in the fifth opening before the S/D region is formed, wherein the conductive structure is used to electrically connect the resistor electrode and the S/D region.

Embodiments of a semiconductor device structure are provided in the disclosure. The semiconductor device structure includes a transistor and a resistor connected in series and formed by an integrated process flow. In particular, a gate electrode of the transistor and a resistor electrode of the resistor are formed in a semiconductor substrate by the same process steps. Therefore, the resistor may have high sheet resistance without using additional masks or process steps. As a result, the associated costs may be reduced, and the performance of the semiconductor device structure may be improved.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a cross-sectional view illustrating a semiconductor device structure, in accordance with some embodiments.

FIG. 2 is a circuit diagram of the semiconductor device structure in FIG. 1.

FIG. 3 is a cross-sectional view illustrating a modified semiconductor device structure, in accordance with some embodiments.

FIG. 4 is a flow diagram illustrating a method of forming a semiconductor device structure, in accordance with some embodiments.

FIG. 5 is a cross-sectional view illustrating an intermediate stage of forming isolation structures and a well region during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 6 is a cross-sectional view illustrating an intermediate stage of forming openings between the isolation structures during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 7 is a cross-sectional view illustrating an intermediate stage of forming a dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 8 is a cross-sectional view illustrating an intermediate stage of forming an electrode layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 9 is a cross-sectional view illustrating an intermediate stage of performing an ion implantation process on the electrode layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 10 is a cross-sectional view illustrating an intermediate stage of performing an ion implantation process on the electrode layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 11 is a cross-sectional view illustrating an intermediate stage of polishing the electrode layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 12 is a cross-sectional view illustrating an intermediate stage of forming source/drain regions during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 13 is a cross-sectional view illustrating an intermediate stage of forming an inter-layer dielectric during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 14 is a cross-sectional view illustrating an intermediate stage of forming a patterned mask over the inter-layer dielectric during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 15 is a cross-sectional view illustrating an intermediate stage of partially removing the inter-layer dielectric and the dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 16 is a cross-sectional view illustrating an intermediate stage of performing an ion implantation process on the electrode layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 17 is a cross-sectional view illustrating an intermediate stage of performing an ion implantation process on the electrode layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 18 is a cross-sectional view illustrating an intermediate stage of forming an opening in the semiconductor substrate during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 19 is a cross-sectional view illustrating an intermediate stage of forming a conductive layer during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 20 is a cross-sectional view illustrating an intermediate stage of forming a conductive structure during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 21 is a cross-sectional view illustrating an intermediate stage of forming source/drain regions during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 22 is a cross-sectional view illustrating an intermediate stage of forming an inter-layer dielectric during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 23 is a cross-sectional view illustrating an intermediate stage of forming a patterned mask over the inter-layer dielectric during the formation of the semiconductor device structure, in accordance with some embodiments.

FIG. 24 is a cross-sectional view illustrating an intermediate stage of partially removing the inter-layer dielectric and the dielectric layer during the formation of the semiconductor device structure, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG. 1 is a cross-sectional view illustrating a semiconductor device structure 300 a, in accordance with some embodiments. As shown in FIG. 1, the semiconductor device structure 300 a includes a transistor 100 and a resistor 200. In the semiconductor device structure 300 a, a plurality of isolation structures 105 a, 105 b and 105 c are disposed in a semiconductor substrate 101, the active region of the transistor 100 is defined by the isolation structures 105 a and 105 b, and the active region of the resistor 200 is defined by the isolation structures 105 b and 105 c, in accordance with some embodiments. It should be noted that the number of isolation structures per semiconductor device structure is not limited to three, and may be less or more.

In some embodiments, the semiconductor device structure 300 a also includes a gate electrode 115 a and source/drain (S/D) regions 121 a, 121 b in the active region of the transistor 100 (i.e., between the isolation structures 105 a and 105 b). The gate electrode 115 a is located between the S/D regions 121 a and 121 b, and the gate electrode 115 a and the S/D regions 121 a, 121 b are disposed in the semiconductor substrate 101.

In some embodiments, the semiconductor device structure 300 a further includes a well region 103 and a resistor electrode 115 b in the active region of the resistor 200 (i.e., between the isolation structures 105 b and 105 c). The well region 103 and the resistor electrode 115 b are disposed in the semiconductor substrate 101, and the resistor electrode 115 b is disposed over the well region 103. In addition, the well region 103 adjoins the isolation structures 105 b and 105 c. It should be noted that the isolation structure 105 b between the active regions of the transistor 100 and the resistor 200 is closer to the resistor electrode 115 b than the gate electrode 115 a, in accordance with some embodiments.

Moreover, the semiconductor device structure 300 a includes a dielectric layer 113′ disposed over the semiconductor substrate 101, in accordance with some embodiments. In particular, the dielectric layer 113′ has a first portion and a second portion below the top surface 101T of the semiconductor substrate 101, the first portion is between the gate electrode 115 a and the semiconductor substrate 101, and the second portion is between the resistor electrode 115 b and the semiconductor substrate 101. In some embodiments, the gate electrode 115 a is separated from the semiconductor substrate 101 by the first portion of the dielectric layer 113′, and the resistor electrode 115 b is separated from the well region 103 in the semiconductor substrate 101 by the second portion of the dielectric layer 113′.

In addition, in some embodiments, the resistor electrode 115 b is separated from the isolation structures 105 b and 105 c by the second portion of the dielectric layer 113′. In some embodiments, the isolation structures 105 a, 105 b and 105 c are covered by the dielectric layer 113′, and the S/D regions 121 a and 121 b are partially covered by the dielectric layer 113′.

Still referring to FIG. 1, the semiconductor device structure 300 a includes an inter-layer dielectric (ILD) 123′ disposed over the dielectric layer 113′, and an interconnect structure 137 disposed over the ILD layer 123′, in accordance with some embodiments. More specifically, the interconnect structure 137 includes a plurality of conductive vias 133 a, 133 b, 133 c and 133 d, and a plurality of conductive layers 135 a, 135 b and 135 c.

In some embodiments, the conductive vias 133 a, 133 b, 133 c and 133 d are disposed in the ILD layer 123′, and the conductive layers 135 a, 135 b and 135 c are disposed over the ILD layer 123′. In some embodiments, the conductive vias 133 a and 133 b penetrate through the ILD layer 123′ and the dielectric layer 113′ to electrically connect the S/D regions 121 a and 121 b, and the conductive vias 133 c and 133 d penetrate through the ILD layer 123′ to electrically connect the resistor electrode 115 b. In particular, the conductive via 133 a is disposed over the S/D region 121 a, and the conductive layer 135 a is disposed over the conductive via 133 a. The S/D region 121 a is electrically connected to the conductive layer 135 a through the conductive via 133 a, and the conductive layer 135 a is used to electrically connect the S/D region 121 a to other devices.

In some embodiments, the conductive via 133 b is disposed over the S/D region 121 b, the conductive via 133 c is disposed over a portion of the resistor electrode 115 b adjacent to the isolation structure 105 b, and the conductive layer 135 b is disposed over the conductive vias 133 b and 133 c. The conductive vias 133 b and 133 c are covered by the conductive layer 135 b. It should be noted that the S/D region 121 b of the transistor 100 is electrically connected to the resistor electrode 115 b of the resistor 200 through the interconnect structure 137 (i.e., the conductive via 133 b, the conductive layer 135 b, and the conductive via 133 c). Therefore, the transistor 100 and the resistor 200 are connected in series.

In some embodiments, the conductive via 133 d is disposed over a portion of the resistor electrode 115 b adjacent to the isolation structure 105 c, and the conductive layer 135 c is disposed over the conductive via 133 d. The resistor electrode 115 b is electrically connected to the conductive layer 135 c through the conductive via 133 d, and the conductive layer 135 c is used to electrically connect the resistor 200 to other devices.

FIG. 2 is a circuit diagram of the semiconductor device structure 300 a in FIG. 1. As shown in FIGS. 1 and 2, the transistor 100 of the semiconductor device structure 300 a may be a P-type metal-oxide-semiconductor (PMOS) transistor 100P, and the PMOS transistor 100P and the resistor 200 are connected in series. Alternatively, the transistor 100 of the semiconductor device structure 300 a may be an N-type metal-oxide-semiconductor (NMOS) transistor 100N, and the NMOS transistor 100N and the resistor 200 are connected in series.

FIG. 3 is a cross-sectional view illustrating a modified semiconductor device structure 300 b, in accordance with some embodiments. Similar to the semiconductor device structure 300 a of FIG. 1, the semiconductor device structure 300 b includes the transistor 100 and the resistor 200. The difference between the semiconductor device structures 300 a and 300 b is the connecting fashion of the transistor 100 and the resistor 200.

As shown in FIG. 3, the semiconductor device structure 300 b includes a conductive structure 145 disposed in the semiconductor substrate 101 and over the isolation structure 105 b, in accordance with some embodiments. In some embodiments, the conductive structure 145 is covered by the ILD layer 123′, and the conductive structure 145 is disposed between the S/D region 121 b of the transistor 100 and the resistor electrode 115 b of the resistor 200. It should be noted that the S/D region 121 b is electrically connected to the resistor electrode 115 b through the conductive structure 145.

In some embodiments, the conductive structure 145 is in direct contact with the S/D region 121 b and the resistor electrode 115 b, and the conductive structure 145 is not covered by the dielectric layer 113′. Moreover, in some embodiments, the conductive vias 133 b and 133 c, and the conductive layer 135 b are not formed in the semiconductor device structure 300 b, and the interconnect structure 137 of the semiconductor device structure 300 b includes the conductive vias 133 a, 133 d and the conductive layers 135 a, 135 c. FIG. 2 may be a circuit diagram representing the semiconductor device structure 300 b shown in FIG. 3.

FIG. 4 is a flow diagram illustrating a method 10 of forming the semiconductor device structure 300 a, and the method 10 includes steps S11, S13, S15, S17, S19, S21, S23 and S25, in accordance with some embodiments. The steps S11 to S25 of FIG. 4 are elaborated in connection with following figures.

FIGS. 5 to 15 are cross-sectional views illustrating intermediate stages in the formation of the semiconductor device structure 300 a, in accordance with some embodiments.

As shown in FIG. 5, the semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate which may include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

Still referring to FIG. 5, the isolation structures 105 a, 105 b, 105 c are formed in the semiconductor substrate 101, and the well region 103 is formed between the isolation structures 105 b and 105 c, in accordance with some embodiments. In some embodiments, the isolation structures 105 a, 105 b and 105 c are shallow trench isolation (STI) structures. In addition, the isolation structures 105 a, 105 b and 105 c may be made of silicon oxide, silicon nitride, silicon oxynitride or another applicable dielectric material, and the formation of the isolation structures 105 a, 105 b and 105 c may include forming a patterned mask (not shown) over the semiconductor substrate 101, etching the semiconductor substrate 101 to form openings (not shown) by using the patterned mask as a mask, depositing a dielectric material in the openings and over the semiconductor substrate 101, and polishing the dielectric material until the semiconductor substrate 101 is exposed.

In some embodiments, the well region 103 is formed by an ion implantation process, and P-type dopants, such as boron (B), gallium (Ga), or indium (In), or N-type dopants, such as phosphorous (P) or arsenic (As), can be implanted in the portion of the semiconductor substrate 101 between the isolation structures 105 b and 105 c to form the well region 103 (The ion implantation process may be performed by using a patterned mask covering the portion of the semiconductor substrate 101 between the isolation structures 105 a and 105 b). The respective step is illustrated as the step S11 in the method 10 shown in FIG. 4.

In some embodiments, the isolation structures 105 a, 105 b and 105 c are formed before the well region 103. In some other embodiments, the well region 103 is formed before the isolation structures 105 a, 105 b and 105 c. In addition, the bottom surface B1 of the well region 103 is higher than the bottom surface B2 of the isolation structures 105 a, 105 b and 105 c, in accordance with some embodiments.

Next, a patterned mask 107 is formed over the semiconductor substrate 101, and the semiconductor substrate 101 is recessed to form openings 110 a and 110 b by using the patterned mask 107 as an etching mask, as shown in FIG. 6 in accordance with some embodiments. In some embodiments, the opening 110 a is located between the isolation structures 105 a and 105 b, and the opening 110 b is located between the isolation structures 105 b and 105 b. The respective step is illustrated as the step S13 in the method 10 shown in FIG. 4.

The patterned mask 107 may be formed by a deposition process and a patterning process. The deposition process for forming the patterned mask 107 may be a chemical vapor deposition (CVD) process, a high-density plasma CVD (HDPCVD) process, a spin-coating process, or another applicable process. The patterning process for forming the patterned mask 107 may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin-coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

After the patterned mask 107 is formed, the portions of the semiconductor substrate 101 exposed by the patterned mask 107 are partially removed by an etching process. The etching process may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the opening 110 b is formed by removing an upper portion of the well region 103, such that the opening 110 b is formed over the resulting well region 103.

In some embodiments, the sidewalls of the isolation structures 105 b and 105 c are partially exposed by the opening 110 b. For example, the isolation structure 105 b has a first sidewall SW1 facing the isolation structure 105 a and a second sidewall SW2 facing the isolation structure 105 c. The first sidewall SW1 is covered by the semiconductor structure 101 while the second sidewall SW2 is partially exposed by the opening 110 b. Moreover, the opening 110 a has a width W1, the opening 110 b has a width W2, and the width W2 is greater than the width W1, in accordance with some embodiments. After the openings 110 a and 110 b are formed, the patterned mask 107 may be removed.

The dielectric layer 113 is deposited over the semiconductor substrate 101, as shown in FIG. 7 in accordance with some embodiments. In some embodiments, the dielectric layer 113 is deposited conformally in the openings 110 a and 110 b, such as on the sidewalls and the bottom surfaces of the openings 110 a and 110 b, and the isolation structures 105 a, 105 b and 105 c are covered by the dielectric layer 113. The respective step is illustrated as the step S15 in the method 10 shown in FIG. 4. After the dielectric layer 113 is formed, reduced openings 110 a′ and 110 b′ are obtained.

In some embodiments, the dielectric layer 113 includes silicon oxide, silicon nitride, silicon oxynitride, or multilayers thereof. In some embodiments, the dielectric layer 113 is made of a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. In addition, the dielectric layer 113 may be deposited by a conformal deposition process, such as a CVD process, an atomic layer deposition (ALD) process, a plasma-enhanced CVD (PECVD) process, another applicable process, or a combination thereof.

After the dielectric layer 113 is formed, an electrode layer 115 is formed over the dielectric layer 113, and the openings 110 a′ and 110 b′ (see FIG. 7) in the semiconductor substrate 101 are filled by the electrode layer 115, as shown in FIG. 8 in accordance with some embodiments. The respective step is illustrated as the step S17 in the method 10 shown in FIG. 4.

In some embodiments, the electrode layer 115 is made of a semiconductor material such as polysilicon. In some embodiments, the electrode layer 115 is deposited over the dielectric layer 113 using a CVD process, an ALD process, a sputtering process, or one or more other applicable processes.

Next, a patterned mask 117 is formed to cover the active region between the isolation structures 105 b and 105 c (i.e., the active region of the subsequently-formed resistor 200), and an ion implantation process 160 is performed on the portion of the electrode layer 115 exposed by the patterned mask 117, as shown in FIG. 9 in accordance with some embodiments. In some embodiments, the portion of the electrode layer 115 over the well region 103 is covered by the patterned mask 117.

Some processes used to form the patterned mask 117 are similar to, or the same as, those used to form the patterned mask 107 (see FIG. 6), and details thereof are not repeated herein. During the ion implantation process 160, P-type dopants, such as boron (B), gallium (Ga), or indium (In), or N-type dopants, such as phosphorous (P) or arsenic (As), are introduced into the electrode layer 115 using the patterned mask 117 as an implantation mask. After the ion implantation process 160, the patterned mask 117 may be removed.

Then, a patterned mask 119 is formed to cover the active region between the isolation structures 105 a and 105 b (i.e., the active region of the subsequently-formed transistor 100), and an ion implantation process 170 is performed on the portion of the electrode layer 115 exposed by the patterned mask 119, as shown in FIG. 10 in accordance with some embodiments. In alternative embodiments, the ion implantation process 170 is performed before the ion implantation process 160. The respective step is illustrated as the step S19 in the method 10 shown in FIG. 4.

Some processes used to form the patterned mask 119 are similar to, or the same as, those used to form the patterned mask 107 (see FIG. 6), and details thereof are not repeated herein. During the ion implantation process 170, P-type dopants, such as boron (B), gallium (Ga), or indium (In), or N-type dopants, such as phosphorous (P) or arsenic (As), are introduced into the electrode layer 115 using the patterned mask 119 as an implantation mask.

It should be noted that the portion of the electrode layer 115 between the isolation structures 105 a and 105 b is heavily doped compared with the portion of the electrode layer 115 between the isolation structures 105 b and 105 c for increased conductivity, in accordance with some embodiments. In some embodiments, the dose amount of the ion implantation process 160 is greater than the dose amount of the ion implantation process 170. After the ion implantation process 170, the patterned mask 119 may be removed. In addition, an annealing process may be used to activate the implanted dopants.

Subsequently, a polishing process is performed on the electrode layer 115 to form the gate electrode 115 a in the opening 110 a′ (see FIG. 7) and the resistor electrode 115 b in the opening 110 b′ (see FIG. 7), as shown in FIG. 11 in accordance with some embodiments. In some embodiments, the polishing process is performed until the dielectric layer 113 is exposed, and the excess portion of the electrode layer 115 over the dielectric layer 113 is removed. The respective step is illustrated as the step S21 in the method 10 shown in FIG. 4.

In some embodiments, the polishing process is a chemical mechanical polishing (CMP) process. In some embodiments, the gate electrode 115 a has a width W3, the resistor electrode 115 b has a width W4, and the width W4 is greater than the width W3. Moreover, the required conductivity of the gate electrode 115 a is higher than the required conductivity of the resistor electrode 115 b. Therefore, as mentioned above, a dopant concentration of the gate electrode 115 a is greater than a dopant concentration of the resistor electrode 115 b.

After the gate electrode 115 a and the resistor electrode 115 b is formed, the S/D regions 121 a and 121 b are formed in the semiconductor substrate 101 and on opposite sides of the gate electrode 115 a, as shown in FIG. 12 in accordance with some embodiments. The S/D regions 121 a and 121 b may be formed by ion implantation and/or diffusion, and an annealing process, such as a rapid thermal annealing (RTA) process, may be used to activate the implanted dopants. The respective step is illustrated as the step S23 in the method 10 shown in FIG. 4.

In some embodiments, the S/D regions 121 a and 121 b, and the well region 103 are doped with one or more P-type dopants, such as boron (B), gallium (Ga), or indium (In). In alternative embodiments, the S/D regions 121 a and 121 b, and the well region 103 are doped with one or more N-type dopants, such as phosphorous (P) or arsenic (As).

An ILD layer 123 is formed over the structure of FIG. 12, as shown in FIG. 13 in accordance with some embodiments. In some embodiments, the ILD layer 123 is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. In addition, the ILD layer 123 may be formed by a CVD process, a physical vapor deposition (PVD) process, an ALD process, a spin-coating process, or another applicable process.

Next, a patterned mask 125 is formed over the ILD layer 123, as shown in FIG. 14 in accordance with some embodiments. In some embodiments, the patterned mask 125 has openings, and portions of the ILD layer 123 are exposed by the openings of the patterned mask 125. Some processes used to form the patterned mask 125 are similar to, or the same as, those used to form the patterned mask 107 (see FIG. 6), and details thereof are not repeated herein.

Then, an etching process is performed on the ILD layer 123 and the dielectric layer 113 using the patterned mask 125 as a mask, as shown in FIG. 15 in accordance with some embodiments. After the etching process, an etched dielectric layer 113′ and an etched ILD layer 123′ with openings 130 a, 130 b, 130 c and 130 d are formed. In some embodiments, openings 130 a and 130 b penetrate through the ILD layer 123′ and the dielectric layer 113′, and the S/D regions 121 a and 121 b are exposed by the openings 130 a and 130 b, respectively. In some embodiments, the openings 130 c and 130 d penetrate through the ILD layer 123, and the resistor electrode 115 b are partially exposed by the openings 130 c and 130 d. After the openings 130 a, 130 b, 130 c and 130 d are formed, an etched ILD layer 123′ and an etched dielectric layer 113′ are obtained.

Referring back to FIG. 1, the interconnect structure 137 is formed over the ILD layer 123′, in accordance with some embodiments. As mentioned above, the interconnect structure 137 includes the conductive vias 133 a, 133 b, 133 c and 133 d, and the conductive layers 135 a, 135 b and 135 c. In some embodiments, the conductive vias 133 a, 133 b, 133 c and 133 d are formed in the openings 130 a, 130 b, 130 c and 130 d, respectively, and the conductive layers 135 a, 135 b and 135 c are formed over the ILD layer 123′ to cover the conductive vias 133 a, 133 b, 133 c and 133 d. The respective step is illustrated as the step S25 in the method 10 shown in FIG. 4.

In some embodiments, the interconnect structure 137 is made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, or a combination thereof. Alternatively, other applicable conductive materials may be used. Moreover, the interconnect structure 137 may be formed by one or more deposition process, and a subsequent patterning process. The deposition process may be a CVD process, a PVD process, an ALD process, a metal organic CVD (MOCVD) process, a sputtering process, a plating process, or another applicable deposition process, and the patterning process may include a photolithography process and an etching process. In some embodiments, the interconnect structure 137 includes multilayers.

FIGS. 16 to 17 are cross-sectional views illustrating intermediate stages in the formation of the semiconductor device structure 300 a, in accordance with some other embodiments.

In alternative embodiments, the ion implantation processes 160 and 170 (see FIGS. 9 and 10) are replaced by ion implantation processes 180 and 190, as shown in FIGS. 16 and 17 in accordance with some embodiments. As shown in FIG. 16, the ion implantation process 180 is performed on the structure of FIG. 8 without using any implantation mask.

Subsequently, a patterned mask 139 is formed to cover the active region between the isolation structures 105 b and 105 c (i.e., the active region of the subsequently-formed resistor 200), and the ion implantation process 190 is performed on the portion of the electrode layer 115 exposed by the patterned mask 139, as shown in FIG. 17 in accordance with some embodiments. Some processes used to form the patterned mask 139 are similar to, or the same as, those used to form the patterned mask 107 (see FIG. 6), and details thereof are not repeated herein.

It should be noted that the portion of the electrode layer 115 between the isolation structures 105 a and 105 b are ion-implanted one time more than the portion of the electrode layer 115 between the isolation structures 105 b and 105 c. Therefore, the dopant concentration of the portion of the electrode layer 115 between the isolation structures 105 a and 105 b is greater than the dopant concentration of the portion of the electrode layer 115 between the isolation structures 105 b and 105 c. As a consequence, the dopant concentration of the gate electrode 115 a is greater than a dopant concentration of the resistor electrode 115 b in the resulting semiconductor device structure 300 a.

FIGS. 18 to 20 are cross-sectional views illustrating intermediate stages in the formation of the modified semiconductor device structure 300 b, in accordance with some embodiments.

As shown in FIG. 18, an etching process is performed on the upper portion of the isolation structure 105 b and the dielectric layer 113 to form an opening 140 after the electrode layer 115 is polished (see FIG. 12), in accordance with some embodiments. The opening 140 may be formed by using a patterned mask (not shown) as an etching mask. In some embodiments, the semiconductor substrate 101 and the resistor electrode 115 b are partially etched to form the opening 140.

Next, a conductive layer 143 is formed over the dielectric layer 113′, and the opening 140 is filled by the conductive layer 143, as shown in FIG. 19 in accordance with some embodiments. In some embodiments, the conductive layer 143 is in direct contact with the resistor electrode 115 b.

In some embodiments, the conductive layer 143 is made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, another applicable conductive material, or a combination thereof. In addition, the conductive layer 143 may be formed by a CVD process, a PVD process, an ALD process, a plating process, a sputtering process, or another applicable process.

After the conductive layer 143 is formed, a planarization process is performed to expose the gate electrode 115 a and the resistor electrode 115 b, and the conductive structure 145 is formed in the semiconductor substrate 101 and over the isolation structure 105 b, as shown in FIG. 20 in accordance with some embodiments. The planarization process for forming the conductive structure 145 may include a CMP process, a grinding process, an etching process, another suitable process, or a combination thereof.

After the planarization process, the top surfaces of the dielectric layer 113′, the gate electrode 115 a, the resistor electrode 115 b, and the conductive structure 145 are substantially coplanar with each other, in accordance with some embodiments. Within the context of this disclosure, the word “substantially” means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

After the gate electrode 115 a and the resistor electrode 115 b is formed, the S/D regions 121 a and 121 b are formed in the semiconductor substrate 101 and on opposite sides of the gate electrode 115 a, as shown in FIG. 21 in accordance with some embodiments. The S/D regions 121 a and 121 b may be formed by ion implantation and/or diffusion, and an annealing process, such as a rapid thermal annealing (RTA) process, may be used to activate the implanted dopants. The respective step is illustrated as the step S23 in the method 10 shown in FIG. 4.

In some embodiments, the S/D regions 121 a and 121 b, and the well region 103 are doped with one or more P-type dopants, such as boron (B), gallium (Ga), or indium (In). In alternative embodiments, the S/D regions 121 a and 121 b, and the well region 103 are doped with one or more N-type dopants, such as phosphorous (P) or arsenic (As).

An ILD layer 123 is formed over the structure of FIG. 21, as shown in FIG. 22 in accordance with some embodiments. In some embodiments, the ILD layer 123 is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. In addition, the ILD layer 123 may be formed by a CVD process, a physical vapor deposition (PVD) process, an ALD process, a spin-coating process, or another applicable process.

Next, a patterned mask 125 is formed over the ILD layer 123, as shown in FIG. 23 in accordance with some embodiments. In some embodiments, the patterned mask 125 has openings, and portions of the ILD layer 123 are exposed by the openings of the patterned mask 125. Some processes used to form the patterned mask 125 are similar to, or the same as, those used to form the patterned mask 107 (see FIG. 6), and details thereof are not repeated herein.

Then, an etching process is performed on the ILD layer 123 and the dielectric layer 113′ using the patterned mask 125 as a mask, as shown in FIG. 24 in accordance with some embodiments. After the etching process, an etched ILD layer 123′ with openings 130 a and 130 d are formed. In some embodiments, the opening 130 a penetrates through the ILD layer 123′ and the dielectric layer 113′, and the S/D regions 121 a and 121 b are exposed by the opening 130 a, respectively. In some embodiments, the opening 130 d penetrates through the ILD layer 123′, and the resistor electrode 115 b are partially exposed by the opening 130 c. After the openings 130 a and 130 d are formed, an etched ILD layer 123′ and an etched dielectric layer 113′ are obtained.

Referring back to FIG. 3, after forming the openings 130 a and 130 d, the interconnect structure 137 is formed over the ILD layer 123′, in accordance with some embodiments. As mentioned above, the interconnect structure 137 includes the conductive vias 133 a, 133 b, 133 c and 133 d, and the conductive layers 135 a, 135 b and 135 c. In some embodiments, the conductive vias 133 a, 133 b, 133 c and 133 d are formed in the openings 130 a, 130 b, 130 c and 130 d, respectively, and the conductive layers 135 a, 135 b and 135 c are formed over the ILD layer 123′ to cover the conductive vias 133 a, 133 b, 133 c and 133 d. The respective step is illustrated as the step S25 in the method 10 shown in FIG. 4.

In some embodiments, the interconnect structure 137 is made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, or a combination thereof. Alternatively, other applicable conductive materials may be used. Moreover, the interconnect structure 137 may be formed by one or more deposition process, and a subsequent patterning process. The deposition process may be a CVD process, a PVD process, an ALD process, a metal organic CVD (MOCVD) process, a sputtering process, a plating process, or another applicable deposition process, and the patterning process may include a photolithography process and an etching process. In some embodiments, the interconnect structure 137 includes multilayers.

As mentioned above, since the connecting fashion of the transistor 100 and the resistor 200 are different between the semiconductor device structures 300 a and 300 b, the openings 130 b and 130 c (see FIG. 15) are not formed in the ILD layer 123′, such that the interconnect structure 137 of the semiconductor device structure 300 b (see FIG. 3) only includes the conductive vias 133 a, 133 d, and the conductive layers 135 a, 135 c. However, in some other embodiments, the interconnect structure 137 of the semiconductor device structure 300 b includes other conductive elements for electrically connecting with other devices.

Embodiments of the semiconductor device structures 300 a and 300 b are provided in the disclosure. The semiconductor device structures 300 a and 300 b include the transistor 100 (e.g., the PMOS transistor 100P or the NMOS transistor 100N) and the resistor 200 connected in series and formed by an integrated process flow. Particularly, the gate electrode 115 a of the transistor 100 and the resistor electrode 115 b of the resistor 200 are formed in the semiconductor substrate 101 by the same process steps. Therefore, the resistor 200 may have high sheet resistance without using additional masks or process steps. As a result, the associated costs may be reduced, and the performance of the semiconductor device structures 300 a and 300 b may be improved.

In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a gate electrode and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.

In another embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a gate electrode and a resistor electrode disposed in a semiconductor substrate. A dopant concentration of the gate electrode is greater than a dopant concentration of the resistor electrode. The semiconductor device structure also includes an isolation structure disposed in the semiconductor substrate. The gate electrode and the resistor electrode are separated by the isolation structure. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.

In yet another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming an isolation structure in a semiconductor substrate, and recessing the semiconductor substrate to form a first opening and a second opening. The first opening and the second opening are on opposite sides of the isolation structure, and a width of the second opening is greater than a width of the first opening. The method also includes forming an electrode layer over the semiconductor substrate. The first opening and the second opening are filled by the electrode layer. The method further includes polishing the electrode layer to form a gate electrode in the first opening and a resistor electrode in the second opening, and forming a source/drain (S/D) region in the semiconductor substrate. The S/D region is between the gate electrode and the isolation structure.

The embodiments of the present disclosure have some advantageous features. By forming a gate electrode of a transistor and a resistor electrode of a resistor in a semiconductor substrate by the same process steps, the resistor may have high sheet resistance without using additional masks or process steps. This significantly reduces the associated costs, and the performance of the semiconductor device structure including the transistor and the resistor may be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps. 

What is claimed is:
 1. A method for preparing a semiconductor device structure, comprising: forming an isolation structure in a semiconductor substrate; recessing the semiconductor substrate to form a first opening and a second opening, wherein the first opening and the second opening are on opposite sides of the isolation structure, and a width of the second opening is greater than a width of the first opening; forming an electrode layer over the semiconductor substrate, wherein the first opening and the second opening are filled by the electrode layer; polishing the electrode layer to form a gate electrode in the first opening and a resistor electrode in the second opening; and forming a source/drain (S/D) region in the semiconductor substrate, wherein the S/D region is between the gate electrode and the isolation structure.
 2. The method for preparing a semiconductor device structure of claim 1, further comprising: forming a well region in the semiconductor substrate before the first opening and the second opening are formed, wherein a bottom surface of the well region is higher than a bottom surface of the isolation structure, and the second opening is formed by removing an upper portion of the well region.
 3. The method for preparing a semiconductor device structure of claim 1, wherein a sidewall of the isolation structure is exposed by the second opening after recessing the semiconductor substrate.
 4. The method for preparing a semiconductor device structure of claim 1, further comprising: depositing a dielectric layer over the semiconductor substrate before the electrode layer is formed, wherein the dielectric layer extends into the first opening and the second opening.
 5. The method for preparing a semiconductor device structure of claim 1, further comprising: performing an ion implantation process on the electrode layer before the electrode layer is polished.
 6. The method for preparing a semiconductor device structure of claim 1, further comprising: forming an inter-layer dielectric (ILD) over the semiconductor substrate; etching the ILD layer to form a third opening exposing the S/D region and a fourth opening exposing the resistor electrode; and forming an interconnect structure in the openings and over the ILD layer, wherein the interconnect structure is used to electrically connect the S/D region and the resistor electrode.
 7. The method for preparing a semiconductor device structure of claim 1, further comprising: etching an upper portion of the isolation structure to form a fifth opening after the electrode layer is polished; and forming a conductive structure in the fifth opening before the S/D region is formed, wherein the conductive structure is used to electrically connect the resistor electrode and the S/D region. 